The present invention relates to a floor-planning apparatus for use in designing a large scale integrated circuit (LSI) hierarchically.
In a conventional floor-planner used in designing LSI hierarchically, by monitoring interconnecting relationships between macros, a floor-plan has been tried out or a schematic wiring has been carried out to estimate the area of an LSI chip. In addition, a process in which functional blocks for high duty driving are used depending on the length of wiring between the macros has been carried out in designing the logic circuit prior to the planning of the floor-plan.
In the foregoing conventional process, since, prior to determining the floor-plan, the interconnection in which the wiring length between the macros will be elongated must be changed to the function block for high duty driving, there is a drawback in that the logic circuit must be designed by taking the floor-plan into account.